Low-Density Parity Check Codes for Error Correction in Nanoscale Memory

The continued scaling of photolithographic fabrication techniques down to 32 nanometers and beyond faces enormous technology and economic barriers. Selfassembled devices such as silicon nanowires or carbon nanotubes show promise to not only achieve aggressive dimensions, but to help address power and other gating issues in system architecture, while potentially helping contain rampant increases in fabrication capital costs. However, assembling high-quality, largescale nanoelectronic circuits (e.g., with Langmuir-Blodgett or related methods) has proven challenging. Among the major challenges are extremely high defect and fault rates in assembled devices. Apart from fabrication errors, nanoscale devices are also more prone to soft errors than microscale devices. Current-day microscale devices (e.g., gates, PLAs, memories) constructed using top-down lithographic techniques have error rates of less than 1% [10]. But computing and storage components built using nanoscale elements (e.g., bistable and switchable organic molecules, carbon nanotubes, single-crystal semiconductor nanowires) may have an order of magnitude higher rates of faults (as high as 10%) [5, 8]. We consider static defects and soft errors separately. Static defects can be handled using testing and reconfiguration [21], though this presents increasing challenges as technology scales. Soft error correction is critical for different nanoscale devices, performing storage (e.g., nanomemory), computation (e.g., nano-ALU) or communication (e.g., nanoscale signal transmitters and receivers). In this paper, we focus on error correction for nanoscale memory. We will concentrate on an architecture that uses nano-PLA blocks and simple nanogates (e.g., majority gate, nand/nor gates) as design components [7]. Because of high soft-error rates, our envisioned nanomemories would also need to employ online error correcting codes (ECCs), as most modern memory subsystems already do [10, 13]. However, for nanomemories with high fault rates, a new type of error correction is desired, since conventional ECC techniques are not directly applicable. The encoders and decoders for Hamming and Hsiao codes, for example, have low encoding and decoding complexity, but also have relatively low error-